Many computing systems such as personal computers, automotive and airplane control, cellular phones, digital cameras, and handheld communication devices use nonvolatile writeable memories to store either data, or code, or both. Such nonvolatile writeable memories include Electrically Erasable Programmable Read-Only Memories ("EEPROMs") and flash Erasable and Electrically Programmable Read-Only Memories ("flash EPROMs" or "flash memories"). Nonvolatility is advantageous for allowing the computing system to retain its data and code when power is removed from the computing system. Thus, if the system is turned off or if there is a power failure, there is no loss of code or data.
The nonvolatile writeable memories often include a plurality of interconnected very large scale integration (VLSI) circuits. These VLSI circuits dissipate power in proportion to the nominal voltage swing of the binary signals applied to the circuits. The industry standard VLSI complementary metal-oxide-semiconductor (CMOS) circuits currently utilize two levels of input/output (I/O) signals, 1.8 volts and 3.0 volts. As the rail-to-rail voltage swing of standard CMOS circuits utilizing the 3.0 volt signal level tends to cause such circuits to dissipate excessive amounts of power and energy over CMOS circuits utilizing the 1.8 volt signal level, the 1.8 volt CMOS circuit would be preferred in an application requiring reduced power consumption.
With the size of many electronic products becoming increasingly smaller, many electronic product designers are currently seeking to minimize power consumption. Generally, reducing the overall magnitude of rail-to-rail voltage swings of CMOS circuits allows a reduction in power consumption. Thus, an electronic architecture that would allow and work with lower input voltage swings without drawing leakage current is desirable. However, many applications of CMOS circuits still use 3.0 volt system power supplies which need to be accommodated. Consequently, an electronic system architectural concept is used whereby the nonvolatile writeable memory circuits operate with industry standard 1.8 volt and 3.0 volt CMOS I/O signal levels and utilize the optimum core supply voltage for the nonvolatile writeable memory core circuits.
Designers of prior art electronic systems incorporating nonvolatile writeable memory have attempted to reduce the overall system power consumption by running the entire system at the 1.8 volt I/O signal level and supply voltage. This increases the power efficiency of the system exclusive of the nonvolatile writeable memory. However, the nonvolatile writeable memory core memory circuits running at the 1.8 volt I/O signal level have a reduced power efficiency due to the inefficiencies of producing high voltages internal to the nonvolatile writeable memory. Thus, to effectively maximize efficiency of the overall electronic system, I/O interface buffers were designed to allow the nonvolatile writeable memory core memory circuits to be operated at a 3.0 volt I/O signal level, while the surrounding system CMOS circuitry is operated at a 1.8 volt I/O signal level. The 3.0 volt I/O nominal signal level can be approximately in the range 2.7 volts to 3.6 volts.
Designers of prior art electronic systems that operated at a 3.0 volt I/0 signal level while using nonvolatile writeable memory used one power supply, commonly known as VCC. In order to prevent corruption of the data of the nonvolatile writeable memory, the prior art electronic systems utilized lockout circuitry. The lockout circuitry locked out spurious write commands to the command port of the nonvolatile writeable memory that were issued when the VCC voltage supply from was below a specified safe level, that level known heretofore as "V-lockout" or VLKO. On all prior art nonvolatile writeable memory devices, this lockout circuitry operated on the general nonvolatile writeable memory device power supply, VCC, only.